1. Field of the Invention
The present invention relates generally to a dc-offset cancelled programmable gain array (PGA) for wireless local area network (WLAN) applications. More specifically, embodiments of the present invention relate to an amplifier circuit with DC-offset cancellation, where a high-pass pole with a large time constant may be switched to a lower or higher frequency.
2. Background Art
The rapid evolution of CMOS technology has accelerated the integration of mixed-signal systems, such as the wireless transceiver on a single chip. In the case of a zero intermediate-frequency (IF) or low IF receiver architecture targeted toward IEEE 802.11 a/b/g WLAN applications, signal levels arriving at the baseband are scaled to around a 0 dBm range for analog-to-digital conversion. FIG. 1 shows a block diagram for a receiver 100 in a dual-receive conversion configuration. The receiver 100 may include a Radio-Frequency (RF) input 105, a Low Noise Amplifier (LNA) 110 followed by a mixer 115 with a Local Oscillator Reference Frequency (LORF) 117, also in the RF range. Due to the difference between the “in-phase” I and the “quadrature” Q signals, mixers 120 and 125 may have different IF reference frequencies (LOIF(I) 122 and LOIF (Q) 127). Baseband channel selection filters 130 and 135 and PGAs 140 and 145 complete the typical low IF receiver block diagram. PGAs 140 and 145 are inverting amplifiers that include a switched-resistor bank for gain control. Terminals 150 and 155 constitute the output. A single synthesizer may synthesize both the IF and the LORF frequencies.
The dynamic-range requirement from the antenna (input terminal 105) to the baseband may approximately equal 0 to 80 dB, with the majority of the gain achieved in the baseband. If the radio front-end offers a 0 to 30 dB gain range, the baseband channel selection filters 130 and 135 and PGAs 140 and 145 have to provide another 0 to 50 dB of controllable gain. With technology scaling, capacitive coupling in a zero IF receiver would increase enough to contribute to the dc-offset problem. The dc-offset may easily saturate the PGA due to a large cascaded gain. For example, in a zero IF receiver, the composite high-pass pole must be around tens of kilohertz (kHz) in order to prevent deep signal damage. The large time constant of such a composite high-pass pole requires a circuit with a large chip-area and an appropriate circuitry to overcome the long dc-offset transient induced in the gain change. This is particularly crucial for IEEE 802.11a and 802.11g applications, where the short preamble for gain settling time is just 8 μs.